Many presently marketed data processing systems have adopted a data format wherein data bits and clock bits are interspersed in a composite serial bit stream. For example, the data may be presented in sequential time intervals (or "bit cells") defined by two clock pulses, with the presence or absence of a pulse between the clock pulses determining the bit cell value. While the clock pulses normally recur at a predetermined rate, predetermined sequences of absent clock pulses are often used as headers to identify the beginning of various fields in the data. There is, however, generally a predetermined maximum number of successive absent clock pulses in such headers.
An example of such a data format is that used in systems compatible with the so-called IBM 3740 data entry system. The IBM 3740 system utilizes diskettes including an index track, a plurality of data tracks, alternate tracks and spare tracks. Each of the tracks is divided into a plurality of sectors or fields. The data within the fields, grouped in bytes, consists of eight consecutive bit cells, the bit cells being time intervals defined by the nominal clock rate. The clock pulses normally recur at 250 Khz, and except during predetermined portions of the header, as will be described, are always present.
Each field in a track is conventionally separated from adjacent fields by "gaps," comprising a predetermined number of bytes comprising all zeros or ones, followed by a predetermined number of bytes comprising all zeros. Address marks are used to identify the beginning of ID and data fields and to synchronize separation and deserializing circuitry with the first byte of each field. Such address marks include unique byte sequences of data and clock pulses. The patterns generally include bit cells having non-occurrences or absences of clock pulses, but the maximum predetermined number of successive absent clock pulses is conventionally three. An index address mark is conventionally located at the beginning of each track comprising a fixed number of bytes in front of the first record. An ID address mark byte is also conventionally located at the beginning of each ID field on the diskette and a data address mark byte is located at the beginning of each data field on the diskette.
Data separation circuitry is utilized to generate, from the composite signal of interpersed clock and data pulses, separated data and clock pulse streams. Such data separation circuitry must be operated in synchronization with the phase of the composite pulse stream, lest the data and clock pulse streams be erroneously interchanged. Various prior systems have depended upon the presence of appropriate gaps to synchronize the data separation circuit with the composite signal. Some such systems interchange the separate bit streams upon detection of a missing pulse in the separated clock pulse stream, utilizing a single monostable multivibrator to establish the bit cell period. Multiplexing schemes are then used in such systems to prevent loss of data. Such schemes, however, require relatively complex circuitry and are generally inadequate. A second monostable is sometimes used in such systems to establish a second bit cell period. One monostable or the other is fired in accordance with the data value of the preceding bit cell to improve the error margin of the system.
Other prior systems have used phase locked loops to provide data separation, the flywheel effect of the phase locked loops maintaining synchronization through sequences of absent clock pulses. These systems, however, generally require relatively lengthy periods to establish synchronization and, further, are slow to respond to timing changes in the composite signal.
Now, however, a data separator has been discovered which avoids such problems by reiterative use of a unique digital algorithm. In the exemplary embodiment to be described below, the next encountered pulse in the composite stream is passed to the clock pulse stream. Pulses from the composite pulse stream occurring during subsequent alternating periodic time intervals are passed to the data pulse stream and to the clock pulse stream, respectively. Absences of clock pulses in the resultant separated clock pulse stream are detected and counted and the above recited steps are repeated after detecting the predetermined number of absences of clock pulses. These and other or similar special techniques and circuitry are preferably included in use of this invention so as to provide separation of the composite bit streams with improved technical and economic criteria.